The invention relates to capacitor digital-to-analog converters (CDACs), and particularly to compensation DACs used to compensate for imperfections in manufacture of capacitive components in a CDAC and for compensating various parasitics therein.
CDACs are well known. The state of the art is generally indicated in "A charge-transfer multiplying digital-to-analog converter" by Albarran and Hodges, IEEE Journal of Solid-State Circuits, Vol. SC-11, pages 772-779, December 1976, incorporated herein by reference. A CDAC uses a binarily weighted array of capacitors (instead of a binarily weighted R/2R resistive divider array) in conjunction with bit switch circuits that respond to binary input signals to convert a digital input word to a corresponding analog output signal. A typical CDAC includes a "main DAC" portion each bit of which includes a pullup MOSFET (Metal Oxide Semiconductor Field Effect Transistor) selectively connecting the capacitor of that bit to a precise reference voltage. Each bit also includes a pulldown MOSFET selectively connecting one electrode of the same capacitor to ground. The other terminal of each of the capacitors of the respective bits is connected to a first charge summing conductor. One of the main commercial uses of CDACs is in successive approximation analog-to-digital converters (ADCs). Such an analog-to-digital converter includes a "trim CDAC" which includes a second charge summing conductor. Resistors in voltage divider circuits in the trim CDAC typically are laser trimmed during manufacture to compensate for minute errors in the main CDAC (which contains no resistors corresponding to the voltage dividers) due to inaccuracies in manufacture of the binarily weighted capacitors of the main CDAC, and also to compensate for various parasitic capacitances associated with "clamp" MOSFETs utilized to precisely charge the first and second charge summing conductors to another reference voltage prior to the conversion operation of the CDAC. In the above-mentioned successive approximation ADCs, when each pullup or pulldown MOSFET of a bit of the main CDAC is actuated, a corresponding bit of the trim CDAC also is actuated, and a minute amount of charge precisely established by laser trimming of the corresponding voltage divider circuit is introduced into the charge summing conductor of the trim CDAC. FIG. 2 and its associated description of commonly assigned patent application "DUAL ANALOG-TO-DIGITAL CONVERTER WITH SINGLE SUCCESSIVE APPROXIMATION REGISTER", by Naylor et al., Ser. No. 308,150, filed on Feb. 8, 1989, incorporated herein by reference, and associated description are generally indicative of the state of the art for so-called trim DACs in CDACs of successive approximation ADCs.
Compensation DACs have been utilized to balance mismatches/inaccuracies in the binarily weighted capacitors of the main DAC and also to compensate for various other effects that have not been well understood such prior trim DACs also have been used for the purpose of "balancing out" effects of mismatches in charge injected into the two charge summing conductors by turn-off of the two clamping MOSFETs, respectively, so that all such charge injection is "common mode" with respect to the two charge summing conductors and the inputs of the comparator connected thereto. Prior compensation DACs also have been used to balance out the effects of coupling high frequency noise from the power supply through the bit switch pulldown MOSFETs, the input capacitances of the comparator of the successive approximation ADC, and parasitic capacitive coupling between the substrate and charge summing conductors, so that all such parasitic high frequency noise coupling is "common mode" with respect to the two charge summing conductors and the comparator inputs connected thereto.
The closest prior art is believed to be indicated by the circuit shown in FIG. 4, referred to subsequently.
The prior trim CDACs have not succeeded in improving the accuracy and/or yield of successive approximation ADCs as much as would be desirable apparently because the error-producing charge injection mechanisms have not been sufficiently well understood to address the task of compensating such mechanisms, and because the effects of such error-causing charge injection mechanisms on circuit operation have not been sufficiently well understood. There remains an unmet need for a more accurate CDAC, having an improved power supply rejection ratio, and particularly a successive approximation ADC utilizing such a more accurate CDAC.